1. Field of the Invention
The present invention relates to semiconductor memory and in particular to the array organization for wide program operations and usage of non-volatile memory.
2. Description of the Related Art
Flash memory is characterized by having asymmetric program and erase units. Erase units, called ERASE BLOCKS, are typically large, on the order of 0.5 Mb or 1 Mb or higher. Program units are usually smaller and depend on the application demands. In NOR-type applications, only 16–32b are programmed at once. This data width historically has been limited by the high cell currents associated with the Channel Hot Electron (CHE) injection program method.
Faster program by wide program data width is preferred for mass storage applications. Program units in NAND memories are significantly larger than in NOR memories, typically about 16 kb. NAND memories use Fowler-Nordheim (F-N) tunneling, which is slower, but requires lower current. Therefore, more cells can be programmed in parallel.
Organization of memory arrays is highly dependent upon the application requirements for program and erase data sizes and upon the physical method by which the memory cells program and erase.
Prior Art—NAND Memory Organization: A cross-section of a typical floating gate memory cell 101 is given in FIG. 1. Charge is stored in the floating gate 80 under the word gate 90. The cell is programmed and erased by F-N tunneling. An example of voltage conditions for program and erase will be given. For program, word gate 90 is raised to about 20V, and the bit diffusions 20 and 21 are biased to 0V. In order to erase, the bit diffusions 20 and 21 may be kept at approximately 0V while the word gate is lowered to −20V.
The NAND array provides maximum array efficiency, as shown in FIG. 2. The memory cell is arranged in series, and the word gates are shared in rows, as word lines (WL). The number of rows R between select transistors 70 and 71 is limited by voltage drop through the column. Conventional NAND memories have 16 or 32 rows. The number of columns C is equivalent to the Page size, usually 16 Kb.
Due to the high WL voltage applied during program, WL program disturb is high. Therefore, all of the cells on a single WL are programmed together in one operation. During erase, all the word lines in a section are selected together and the erase block size is R×C.
In summary, the main characteristic of the NAND organization is that all of the cells on the single WL belong to the same erase block.
Prior Art—Twin MONOS: In contrast to the NAND cell operation, the Twin MONOS cell, which was introduced in U.S. Pat. No. 6,255,166 to Ogura et al (assigned to the same assignee as the present invention and herein incorporated in its entirety), uses its unique second control gate (CG) in order to modulate erase selection. A cross-section of the Twin MONOS cell is shown in FIG. 3. This double density cell has two memory storage regions in a single cell. Word gates 901 and 902 are formed by normal lithography. Control gates 11, 12, 13, and 14 are formed by sidewall polysilicon. Neighboring sidewalls 12 and 13 are electrically connected together. Charge is stored in two separate trap regions 602 and 603 under the 2 separate control gates 12 and 13, respectively.
The memory organization of a diffusion bit array was also disclosed in U.S. Pat. No. 6,255,166. In this memory arrangement, the CG lines run in parallel with the Bit Lines (BL) and orthogonal to the Word Lines. There are no contacts for BL in the high density memory array region itself. FIG. 4 gives a schematic representation of the diffusion bit array. Although CG contacts are taken on the opposite side of the memory array from the BL labels in this figure, the actual layout implementation can vary, depending on the layout design rule constraints. In very high density arrays, it is most likely that CG contacts will alternate even/odd on both sides of the memory array. BL contacts will also most likely alternate in the same even/odd or odd/even manner, depending on how the stitch process is designed. U.S. Pat. No. 6,759,290 to Ogura et al, assigned to the same assignee as the present invention and herein incorporated by reference in its entirety, is directed towards some examples of stitch and select implementations in a twin MONOS memory array.
In the Twin MONOS cell, erase can be performed by hot hole injection and F-N tunneling, but hot hole injection is preferred because of the lower voltage requirement and faster operation time.
Several Twin MONOS memory cells may be selected in parallel in the same way as for conventional memories. A decode area may select one column in 4 columns, or 8, 16, or 32 memory columns and connect the selected column to a single sense amplifier or page buffer. In addition to the conventional column decode methods, the Twin MONOS cell's dual-bit characteristic gives a further unique option for memory selection. When a single memory column is selected, there are two additional ways that the Twin MONOS cells may be selected. These methods have already been described in U.S. Pat. No. 6,643,172 to Ogura, assigned to the same assignee as the present invention and herein incorporated by reference in its entirety, and are called single-sided and double-sided selection methods. In the single-sided method, when a column is selected, only a single memory area would be selected in one operation, for example memory area 602 under CG[1] 802. In the double-sided selection method, when a column is selected, both memory areas under the same CG line would be selected at the same time in a single operation, for example memory area 602 and memory area 603 under CG[1] 802.
The advantage of the double-sided selection method is that more cells can be selected in parallel for higher program and read bandwidth. However, the decode area is more complicated, because the two bit line columns BL[0] 401 and BL[2] 403 on opposite sides of the selected column BL[1] 402 will need to be selected and connected to two sense amplifiers or page buffers during read and program. In the case that the column selection is 8, for double-sided select, we say choose 2 bits in 8 columns, and for single-sided select, we say choose 1 bit in 8 columns.
U.S. Pat. Nos. 6,707,720 and 6,707,742 to Kamei et al and 6,710,399 to Kamei are directed towards a Twin MONOS memory cell array organization for NOR type applications. The memory organization is shown in FIG. 5. This memory array is arranged in the diffusion bit array type with CG and BL's running in parallel and orthogonal to the WL, and sectors are defined to be vertical and narrow, because the data width is only on the order of 16b. The column decode is fixed to one in 4 columns in order to minimize width of each sector. The array organization has bit line select transistors and CG lines are connected horizontally. To reduce bit line and control gate line resistance, both are stitched to metal at regular intervals. The target RC delay is less than 10 microseconds. With this arrangement, the number of cells that can be programmed in parallel in a single erase block is only K, the number of I/O. In this arrangement, all of the columns in a sector are selected together to form an erase block. This organization does not take advantage of the inherent ability of the Twin MONOS cell to select individual cells on a single word line during erase.